ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 0B
Register Name sts_priority_table
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit No.
[7:4]
[3:0]
Description
Note used
2nd highest priority validated
Reports the input channel number of the 2nd
highest priority validated source.
Note that if an input is valid and it does not appear
in this field, then the input may have been
disallowed in register 30, 31h.
Register 4B, bit 4 must be set to ‘1’ for correct
setting and reporting of the T4 DPLL priorities.
(RO) Bits [15:8] of the
validated priority table.
Default Value 0000 0000
Bit 3
Bit 2
Bit 1
Bit 0
2nd highest priority validated source
Bit Value Value Description
-
-
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Less than 2 valid sources available.
Input I1 is the 2nd highest priority valid source.
Input I2 is the 2nd highest priority valid source.
Input I3 is the 2nd highest priority valid source.
Input I4 is the 2nd highest priority valid source.
Input I5 is the 2nd highest priority valid source.
Input I6 is the 2nd highest priority valid source.
Input I7 is the 2nd highest priority valid source.
Input I8 is the 2nd highest priority valid source.
Input I9 is the 2nd highest priority valid source.
Input I10 is the 2nd highest priority valid source.
Input I11 is the 2nd highest priority valid source.
Input I12 is the 2nd highest priority valid source.
Input I13 is the 2nd highest priority valid source.
Input I14 is the 2nd highest priority valid source.
Not used.
Address(hex): 0C
Register Name sts_current_DPLL_frequency
[7:0]
Description
(RO) Bits [7:0] of the current
DPLL frequency.
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
current_DPLL_frequency[7:0]
Bit No.
[7:0]
Description
Bits [7:0] of current_DPLL_frequency
*When Bit 4 of register 4B = 0 the frequency of the
Monitor DPLL is reported.
When this Bit 4 = 1 the frequency of the T4 DPLL is
reported.
Bit Value
-
Value Description
See register description of
sts_current_DPLL_frequency at address 0D hex.
Address(hex): 0D
Register Name
Bit 7
sts_current_DPLL_frequency
[15:8]
Bit 6
Bit 5
Description
(RO) Bits [15:8] of the current
DPLL frequency.
Bit 4
Bit 3
Bit 2
current_DPLL_frequency[15:8]
Default Value 0000 0000
Bit 1
Bit 0
Bit No.
[7:0]
Description
current_DPLL_frequency[15:8]
This value in this register is combined with the value
in register 0C and register 07 to represent the
current frequency offset of the DPLL.
When bit 4 of register 4B = 0 the frequency of the
Monitor DPLL path is reported.
When this Bit 4 = 1 the frequency of the T4 DPLL is
reported. The value is actually the DPLL integral
path value so it can be viewed as an average
frequency, where the rate of change is related to the
DPLL bandwidth.
Bit Value
-
Value Description
In order to calculate the ppm offset of the DPLL
with respect to the crystal oscillator frequency,
the value in register 07, 0D & 0C need to be
concatenated. This value is a 2's complement
signed integer. The value multiplied by
0.0003068 dec will give the value in ppm offset
with respect to the XO frequency, allowing for
any crystal calibration that has been performed,
via registers 3C & 3D. If Bit 3 of register 3B is
High then this value will freeze if the DPLL has
been pulled to its min or max frequency.
Revision 3.00 April 2007 © Semtech Corp.
Page 38
www.semtech.com
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