ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
Table 11. Register Map Description (continued).
FINAL
Addr. Parameter Name
(Hex)
05 sts_interrupts
(continued)
Description
Bits (7:6) Unused
Bit 5
SEC2DIFF (sts_interrupts bit 5)
Default
Value (bin)
Bit 4
Bit 3
SEC1DIFF (sts_interrupts bit 4)
SEC2 (sts_interrupts bit 3)
XX0000XX
Bit 2
SEC1 (sts_interrupts bit 2)
Bits (1:0) Unused
06
Bits 7
Operating mode (sts_interrupts bit 15)
Bit 6
Main ref failed (sts_interrupts bit 14)
Bits (5:1) Unused
00XXXXX0
09 sts_operating_mode
Bit 0
SEC 3 (sts_interrupts bit 8)
This read-only register holds the current operating state of the main state machine. Figure 10
show how the values of the 'operating state' variable match with the individual states.
Bits (7:3) Unused
sts_priority_table
Bits (2:0)
001
010
100
110
101
111
State
Freerun (default)
Holdover
Locked
Pre-locked
Pre-locked2
Phase lost
This is a 16-bit read-only register.
XXXXX001
Bits (15:12) Third-highest priority valid source: this is the channel number of the input reference
source which is valid and has the next-highest priority to the second-highest-priority valid source.
Bits (11:8) Second-highest priority valid source: this is the channel number of the input reference
source which is valid and has the next-highest priority to the highest-priority valid source.
Bits (7:4) Highest-priority valid source: this is the channel number of the input reference source
which is valid and has the highest priority; it may not be the same as the currently-selected
reference source (due to failure history or changes in programmed priority).
Bits (3:0) Currently-selected reference source: this is the channel number of the input reference
source which is currently input to the DPLL.
0A
0B
sts_curr_inc_offset
0C
0D
07
Note that these registers are updated by the state machine in response to the contents of the
cnfg_ref_selection_priority register and the ongoing status of individual channels; channel
number '0000', appearing in any of these registers, indicates that no channel is available for that
priority.
Bits (7:4) Highest-priority valid source (sts_priority_table bits (7:4))
Bits (3:0) Currently selected reference source (sts_priority_table bits (3:0))
Bits (7:4) 3rd-highest-priority valid source (sts_priority_table bits (15:12))
Bits (3:0) 2nd-highest-priority valid source (sts_priority_table bits (11:8))
This read-only register contains a signed-integer value representing the 19 significant bits of the
current increment offset of the digital PLL. The register may be read periodically to build up a
historical database for later use during holdover periods (this would only be necessary if an
external oscillator which did not meet the stability criteria described in Local Oscillator Clock
section is used). The register will read 00000000 immediately after reset.
Bits (7:0) sts_curr_inc_offset bits (7:0)
Bits (7:0) sts_curr_inc_offset bits (15:8)
Bits (7:3) Unused
Bits (2:0) sts_curr_inc_offset bits (18:16)
00000000
00000000
00000000
00000000
XXXXX000
Revision 2.01/December 2005 Semtech Corp.
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