ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
FINAL
Table 11. Register Map Description (continued).
Addr. Parameter Name
(Hex)
38 cnfg_output_enable
Description
This register contains several individual configuration fields, as follows:
Default
Value (bin)
0X0XX1XX
Bit 7
=1
=0
O1 output frequency set to 311.04 MHz
O1 output frequency set by Address 3A (5:4) (default)
Bit 6
Unused. Must be set to '0' during initialisation.
Bit 5
=1
=0
SONET mode selected for Dig1
SDH mode selected for Dig1 (default)
- see register cnfg_O1_output_frequencies
Bits (4:3) Unused. Must be set to '0' during initialisation.
Bit 2
=1
=0
Output port O2 enabled (19.44 MHz) (default)
Output port O2 disabled
Bits (1:0) Unused. Must be set to '0' during initialisation.
Note: "Disabled" means the output port holds a static logic value (the port is not Tri-stated).
39 cnfg_O1_output_frequencies This register holds the frequency selections for each output port, as detailed below.
XX00XXXX
Bits (7:6) Unused
Bits (5:4)
00
01
10
11
Dig1
1544 kHz/2048 kHz (default)
3088 kHz/4096 kHz
6176 kHz/8192 kHz
12352 kHz/16384 kHz
Bits (3:2) Unused
Bits (1:0) Unused
3A cnfg_differential_output
For Dig1 the frequency values are shown for SONET/SDH. They are selected via the SONET/SDH
bits in register cnfg_output_enable.
This register holds the frequency selections and the port-technology type for the differential
output O1, as detailed below.
XX00XX10
Bits (7:6) Unused
Bits (3:2) Unused
3B cnfg_bandwidth
Bits (5:4)
00
01
10
11
O1
38.88 MHz (default)
19.44 MHz
155.52 MHz
Dig1
Bits (1:0)
00
01
10
11
O1
Port disabled
PECL-compatible
LVDS-compatible (default)
Unused
This register contains information used to control the operation of the digital PLL. When
bandwidth selection is set to automatic, the DPLL will use the acquisition bandwidth setting
when out of lock, and the normal/locked bandwidth setting when in lock. When set to manual,
the DPLL will alway use the normal/locked bandwidth setting.
0111X101
Bit 7
=1
=0
Automatic operation
Manual operation (default)
Bits (6:4)
000
001
010
011
100
101
110
111
Acquisition bandwidth
0.1 Hz
0.3 Hz
0.5Hz
1.0 Hz
2.0 Hz
4.0 Hz
8.0 Hz
17 Hz (default)
Bit (2:0)
000
001
010
011
100
101
110
111
Loop bandwidth
0.1 Hz
0.3 Hz
0.5 Hz
1.0 Hz
2.0 Hz
4.0 Hz (default)
8.0 Hz
17 Hz
Bit 3
Unused
Revision 2.01/December 2005 Semtech Corp.
26
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