ACS8515REV2.1T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8515REV2.1T' PDF : 50 Pages View PDF
ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
Table 11. Register Map Description (continued).
FINAL
Addr. Parameter Name
(Hex)
cnfg_mode
34
cnfg_control3
35
cnfg_differential_inputs
36
Description
This register contains several individual configuration fields, as detailed below:
Default
Value (bin)
Bit 7
=1 Auto 2 kHz Sync Enable: External 2 kHz Sync will be enabled only when the source is locked
to 6.48 MHz. Otherwise it will be disabled. (default).
=0 Auto 2 kHz Sync Disable: The user controls this function using bit 3 of this register, as
described below.
Bit 6
=1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds. (default).
=0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset by
software.
Bit 5
=1 Rising Clock Edge selected: The device will reference to the rising edge of the external
oscillator signal.
=0 Falling Clock Edge selected: The device will reference to the falling edge of the external
oscillator signal (default).
Bit 4
Unused. Must be set to '0' during initialisation.
Bit 3
=1 External 2 kHz Sync Enable: The device will align the phase of its internally generated
Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of the signal supplied
to the Sync2k pin. This input should be from the 2 kHz Multi-Frame Sync of an ACS8510.
=0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin (default).
110X00X0
(SONSDHB=0)
110X01X0
(SONSDHB=1)
Bit 2
=1 SONET mode: The device expects the input frequency of any input channel given the value
'0001' in the cnfg_ref_source_frequency register to be 1544 kHz.
=0 SDH mode: The device expects the input frequency of any input channel given the value
'0001' in the cnfg_ref_source_frequency register to be 2048 kHz.
At start up or reset the bit value will be defaulted to the setting of pin SONSDHB. This setting
can subsequently be altered by changing this bit value.
Bit 1
Unused
Bit 0
= 1 Revertive Mode: The device will switch to the highest priority source shown in
sts_priority_table register, bits (7:4).
= 0 Non-revertive Mode: The device will retain the presently selected source (default).
Bits (7:6) Unused
Bits (5:4) Must be set to '10' during initialisation.
XX00XXXX
Bits (3:0) Unused
This register contains two individual configuration fields
Bits (7:2) Unused
Bit 1
=1
=0
Input SEC2DIFF is PECL compatible (default)
Input SEC2DIFF is LVDS compatible
XXXXXX10
Bit 0
=1
=0
Input SEC1DIFF is PECL compatible
Input SEC1DIFF is LVDS compatible (default)
Revision 2.01/December 2005 Semtech Corp.
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