ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 34
Register Name cnfg_input_mode
FINAL
DATASHEET
Description
(Bit 1 RO, otherwise R/W)
Default Value
Register controlling various input
modes of the device.
1100 0010*
Bit 7
Bit 6
Bit 5
auto_extsync_ phalarm_time- XO_edge
en
out
Bit 4
Bit 3
man_holdover extsync_en
Bit 2
ip_sonsdhb
Bit 1
Bit 0
master_slaveb reversion_mode
Bit No.
Description
Bit Value Value Description
7
auto_extsync_en
Bit to enable automatic enabling of the external
Frame Sync input when locked to source defined in
Reg. 7C Bits [3:0] (Sync_reference_source).
6
phalarm_timeout
Bit to enable the automatic time-out facility on
phase alarms. When enabled, any source with a
phase alarm set will have its phase alarm cancelled
after 128 seconds.
5
XO_edge
If the 12.800 MHz oscillator module connected to
REFCLK has one edge faster than the other, then for
jitter performance reasons, the faster edge should
be selected. This bit allows either the rising edge or
the falling edge to be selected.
4
man_holdover
Bit to select whether or not the Holdover frequency
is taken directly from Reg. 3E/Reg. 3F/Reg. 40
(cnfg_holdover_frequency). If this bit is set then it
overrides any other Holdover control bits.
3
extsync_en
Bit to select whether or not the T0 DPLL will look for
a reference Sync pulse on the SYNC2K input pin.
Even though this bit may enable the external Sync
reference, it may be disabled according to
auto_extsync_en.
2
ip_sonsdhb
Bit to configure input frequencies to be either
SONET or SDH derived. This applies only to
selections of 0001 (bin) in the
cnfg_ref_source_frequency registers when the
input frequency is either 1544 kHz or 2048 kHz.
Note...this bit affects the SONET/SDH output on
TO9-refer to Reg. 64 Bit 4 and Reg. 35 Bit 4.
*The default value of this bit is taken from the value
of the SONSDHB pin at power-up.
0
External Frame Sync enabled/disabled according to
extsync_en.
1
External Frame Sync enabled if extsync_en = 1 AND
T0 DPLL locked to source assigned to
Sync_reference_source.
0
Phase alarms on sources only cancelled by
software.
1
Phase alarms on sources automatically time out.
0
Device uses the rising edge of the external
oscillator.
1
Device uses the falling edge of the external
oscillator.
0
Holdover frequency is determined automatically.
1
Holdover frequency is taken from
cnfg_holdover_frequency register.
0
No external Sync signal- SYNC2K pin ignored.
1
External Sync derived from SYNC2K pin according to
auto_extsync_en.
0
SDH- inputs set to 0001 expected to be 2048 kHz.
1
SONET- inputs set to 0001 expected to be
1544 kHz.
Revision 3.02/October 2005 © Semtech Corp.
Page 83
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