ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 34 (cont...)
Register Name cnfg_input_mode
FINAL
DATASHEET
Description
(Bit 1 RO, otherwise R/W)
Default Value
Register controlling various input
modes of the device.
1100 0010*
Bit 7
Bit 6
Bit 5
auto_extsync_ phalarm_time- XO_edge
en
out
Bit 4
Bit 3
man_holdover extsync_en
Bit 2
ip_sonsdhb
Bit 1
Bit 0
master_slaveb reversion_mode
Bit No.
Description
Bit Value Value Description
1
master_slaveb (R/O)
Bit to reflect the value of the MASTSLVB pin.
*As this always reflects the value on the pin, the
default value of this bit will be according to the
value on the pin at power-up. For software control,
set MASTSLVB pin to Master mode at all times and
program the individual registers (as per Value
Description) to give Master or Slave mode
functionality.
0
reversion_mode
Bit to select Revertive/Non-revertive mode. When in
Non-revertive mode, the device will not
automatically switch to a higher priority source,
unless the current source fails. When in Revertive
mode the device will always select the highest
priority source.
0
Slave mode.
I11 set to highest priority.
T0 DPLL set to acquisition bandwidth.
Revertive mode enabled.
Phase Build-out disabled.
1
Master mode.
I11 priority, T0 DPLL bandwidth, Revertive mode,
Phase Build-out, all as programmed in the registers.
0
Non-revertive mode.
1
Revertive mode.
Address (hex): 35
Register Name cnfg_T4_path
Description
Register to configure the inputs Default Value 0100 0000
and other features in the T4 path.
Bit 7
Bit 6
lock_T4_to_T0 T4_dig_feed-
back
Bit 5
Bit 4
T4_op_from_T0
Bit 3
Bit 2
Bit 1
T4_forced_reference_source
Bit 0
Bit No.
Description
Bit Value Value Description
7
lock_T4_to_T0
Bit selects either the T4 direct inputs, or T0 DPLL as
the input of the T4 path. This allows the T4 DPLL to
be used to produce different sets of frequencies to
the T0 DPLL but still maintain lock.
6
T4_dig_feedback
Bit to select digital feedback mode for the T4 DPLL.
5
Not used.
4
T4_op_from_T0
0
T4 path locks independently from the T0 path.
1
T4 DPLL locks to the output of the T0 DPLL.
0
T4 DPLL in analog feedback mode.
1
T4 DPLL in digital feedback mode.
-
-
0
T08 and T09 will be generated from T4 DPLL
1
T08 and T09 will be generated from T0 DPLL
Revision 3.02/October 2005 © Semtech Corp.
Page 84
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