ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Outputs
The ACS8525A delivers four output signals on the
following ports: Two clocks, one each on ports Output O1
and Output O2; and two Sync signals, on ports FrSync and
MFrSync. Output O1 and Output O2 are independent of
each other and are individually selectable. Output 01 is a
differential port (pins O1POS and O1NEG), and can be
clocks are selectable from a range of pre-defined spot
frequencies/port technologies, as defined in Tables 6 and
7.
Outputs O1 & O2 Frequency Configuration Steps
The output frequency selection is performed in the
following steps:
selected PECL or LVDS. Output O2 (pin O2) and the Sync 6. Refer to Table 8, Frequency Divider Look-up, to
outputs are TTL/CMOS.
choose a set of output frequencies.
The two Sync outputs, FrSync (8 kHz) and MFrSync
(2 kHz), are derived from DPLL1.
7. Refer to the Table 8 to determine the required APLL
frequency to support the frequency set.
PECL/LVDS Output Port Selection
The choice of PECL or LVDS compatibility for Output 01 is
programmed via the cnfg_differential_output register,
Reg. 3A.
8. Refer to Table 9, APLL1 Frequencies, and Table 10,
APLL2 Frequencies, to determine in what mode
DPLL1 and DPLL2 need to be configured, considering
the output jitter level.
Output Frequency Selection and PLL Configuration
The output frequency at many of the outputs is controlled
by a number of inter-dependent parameters (refer to “PLL
Architecture” on page 14). The frequencies of the output
9. Refer to Table 11, O1 and O2 Output Frequency
Selection, and the column headings in Table 8,
Frequency Divider Look-up, to select the appropriate
frequency from either of the APLLs on each output as
required.
Table 6 Output Reference Source Selection Table
Port
Name
Output Port
Technology
Frequencies Supported
Output
O1
Output
O2
LVDS/PECL
(LVDS default)
TTL/CMOS
Frequency selection as per Table 7 and Table 11
FrSync TTL/CMOS
FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.
MFrSync TTL/CMOS
MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.
Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default
Table 7 Output Frequency Selection
Frequency (MHz, unless stated otherwise)
2 kHz
2 kHz
8 kHz
8 kHz
DPLL1 Mode
DPLL2 Mode
77.76 MHz Analog
-
Any digital feedback mode
-
77.76 MHz Analog
-
Any digital feedback mode
-
APLL2 Input Mux
-
-
-
-
Jitter Level (Typ)
rms p-p
(ps) (ns)
60
0.6
1400 5
60
0.6
1400 5
Revision 1.00/September 2007 © Semtech Corp.
Page 22
www.semtech.com
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