ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
Table 8 Frequency Divider Look-up
FINAL
DATASHEET
Transmission Rate
OC-N Rates
E3
APLL Frequency APLL/2 APLL/4 APLL/6 APLL/8 APLL/12 APLL/16 APLL/48 APLL/64
311.04
155.52 77.76 51.84
38.88 25.92
19.44 6.48
4.86
274.944
137.472 68.376
-
34.368
-
17.184 5.728
4.296
DS3
178.944
89.472 44.736
-
22.368
-
11.184 3.728
2.796
24DS1
16E1
16DS1
148.224
131.072
98.816
74.112
65.536
49.408
37.056 24,704 18.528 12.352 9.264
32.768 21.84533 16.384 10.92267 8.192
24.704 16.46933 12.352 8.234667 6.176
3.088
2.316
2.730667 2.048
2.058667 1.544
12E1
98.304
49.152 24.576 16.384 12.288 8.192
6.144 2.048
1.536
Note...All frequencies in MHz
Table 9 APLL1 Frequencies
APLL1 Frequency
Synthesis/MUX setting for
APLL1 input
311.04
Normal (digital feedback)
311.04 MHz
Normal (analog feedback)
98.304 MHz
12E1 (digital feedback)
131.072 MHz
16E1 (digital feedback)
148.224 MHz
24DS1 (digital feedback)
98.816 MHz
16DS1 (digital feedback)
-
Do not use
-
Do not use
DPLL1 Frequency Control Register Bits
Reg. 65 Bits[2:0]
000
001
010
011
100
101
110
111
Output Jitter Level
ns (p-p)
<0.5
<0.5
<2
<2
<2
<2
-
-
Note...If using Synthesis for inputs to both APLL1 and APLL2, then they must both use the same synthesis settings.
Table 10 APLL2 Frequencies
APLL2
Frequency
DPLL Mode
DPLL2 Forward
DFS Frequency
(MHz)
DPLL2 Freq Control
Register Bits
Reg. 64 Bits [2:0]
APLL2 Input from
DPLL1 or 2.
Reg. 65 Bit 6
311.04 MHz DPLL2-Squelched 77.76
311.04 MHz DPLL2-Normal 77.76
98.304 MHz DPLL2-12E1
24.576
131.072 MHz DPLL2-16E1
32.768
148.224 MHz DPLL2-24DS1
37.056
(2*18.528)
000
0 (DPLL2 enabled)
001
0 (DPLL2 enabled)
010
0 (DPLL2 enabled)
011
0 (DPLL2 enabled)
100
0 (DPLL2 enabled)
DPLL1 + Synthesis
Freq to APLL2
Register Bits
Reg. 65 Bits [5:4]
Output Jitter
Level ns (p-p)
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
Revision 1.00/September 2007 © Semtech Corp.
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