ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
Table 10 APLL2 Frequencies (cont...)
FINAL
APLL2
Frequency
DPLL Mode
DPLL2 Forward
DFS Frequency
(MHz)
DPLL2 Freq Control
Register Bits
Reg. 64 Bits [2:0]
APLL2 Input from
DPLL1 or 2.
Reg. 65 Bit 6
98.816 MHz DPLL2-16DS1
274.944 MHz DPLL2-E3
178.944 MHz DPLL2-DS3
98.304 MHz DPLL1-12E1
131.072 MHz DPLL1-16E1
148.224 MHz DPLL1-24DS1
98.816 MHz DPLL1-16DS1
24.704
68.736
(2*34.368)
44.736
-
-
-
-
101
0 (DPLL2 enabled)
110
0 (DPLL2 enabled)
111
0 (DPLL2 enabled)
XXX
1 (DPLL1 enabled)
XXX
1 (DPLL1 enabled)
XXX
1 (DPLL1 enabled)
XXX
1 (DPLL1 enabled)
DATASHEET
DPLL1 + Synthesis
Freq to APLL2
Register Bits
Reg. 65 Bits [5:4]
Output Jitter
Level ns (p-p)
XX
<0.5
XX
<0.5
XX
<0.5
00
<2
01
<2
10
<2
11
<2
Table 11 O1 and O2 Output Frequency Selection
Output Frequency for given “Value in Register” for each Output Port’s Cnf_output_frequency Register
Value in Register
Output O2
Reg. 61 Bits [3:0]
Output O1
Reg. 62 Bits [7:4]
0000
Off
Off
0001
2 kHz
2 kHz
0010
8 kHz
8 kHz
0011
Digital2
APLL1/2
0100
Digital1
Digital1
0101
APLL1/48
APLL1/1
0110
APLL1/16
APLL1/16
0111
APLL1/12
APLL1/12
1000
APLL1/8
APLL1/8
1001
APLL1/6
APLL1/6
1010
APLL1/4
APLL1/4
1011
APLL2/64
APLL2/64
1100
APLL2/48
APLL2/48
1101
APLL2/16
APLL2/16
1110
APLL2/8
APLL2/8
1111
APLL2/4
APLL2/4
Revision 1.00/September 2007 © Semtech Corp.
Page 28
www.semtech.com
Share Link: 
