ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Table 17 Register Map
FINAL
DATASHEET
Register Name
Data Bit
RO = Read Only
R/W = Read/Write
7 (msb)
6
5
4
3
2
1
0 (lsb)
chip_id (RO)
00 4E
chip_id[7:0], 8 LSBs of Chip ID
01 21
chip_id[15:8], 8 MSBs of Chip ID
chip_revision (RO)
02 00
chip_revision[7:0]
test_register1 (R/W)
03 14 Phase_alarm Disable_180
(RO)
Resync_
analog
Set to 0
8K Edge
Polarity
Set to 0
Set to 0
sts_current_DPLL_frequency [7:0] 0C 00
Bits [7:0] of sts_current_DPLL_frequency
(RO)
[15:8] 0D 00
Bits [15:8] of sts_current_DPLL_frequencyy
[18:16] 07 00
Bits [18:16] of sts_current_DPLL_frequency
sts_reference_sources (RO)
11 22
Alarm Status on inputs:SEC1 & 2
No Activity
SEC2
No Activity
SEC1
cnfg_ref_source_frequency SEC1 22 00 divn_SEC1
lock8k_SEC1
reference_source_frequency_SEC1
(R/W)
SEC2 23 00 divn_SEC2
lock8k_SEC2
reference_source_frequency_SEC2
cnfg_input_mode (R/W)
34 C2 auto_extsync_
en
XO_ edge
ip_sonsdhb
cnfg_DPLL2_path (R/W)
35 40
cnfg_dig_outputs_sonsdh (R/W) 38 14
dig2_sonsdh dig1_sonsdh
cnfg_digtial_frequencies (R/W) 39 08
digital2_frequency
digital1_frequency
cnfg_differential_output (R/W) 3A C2
Output O1 _LVDS_PECL
cnfg_auto_bw_sel
3B 98 auto_BW_sel
DPLL1_lim_int
cnfg_nominal_frequency [7:0] 3C 99
Bits[7:0] of cnfg_nominal_frequency
(R/W)
[15:8] 3D 99
Bits[15:8] of cnfg_nominal_frequency
cnfg_DPLL_freq_limit (R/W) [7:0] 41 FF
Bits[7:0] of cnfg_DPLL_freq_limit
cnfg_DPLL_freq_limit (R/W) [9:8] 42 03
Bits[9:8] cnfg_DPLL_freq_limit
cnfg_freq_divn (R/W)
[7:0]. 46 FF
divn_value [7:0] (divide Input frequency by n)
[13:8] 47 3F
divn_value [13:8] (divide Input frequency by n)
cnfg_registers_source_select
(R/W)
4B 00
DPLL1_DPLL2
_select
cnfg_freq_lim_ph_loss
4D
freq_lim_ph_
loss
cnfg_upper_threshold (R/W)
50 06
upper_threshold_value (Activity alarm, Leaky Bucket - set threshold)
cnfg_lower_threshold (R/W)
51 04
lower_threshold_value (Activity alarm, Leaky Bucket - reset threshold)
cnfg_bucket_size (R/W)
52 08
bucket_size_value (Activity alarm, Leaky Bucket - size)
cnfg_decay_rate (R/W)
53 01
decay_rate_value (Activity
alarm, Leaky Bucket - leak rate)
cnfg_output_frequency(R/W) (O2) 61 0A
output_freq_O2
(O1) 62 00
output_freq_O1
(MFrSync/FrSync) 63 C0 MFrSync_en FrSync_en
cnfg_DPLL2_frequency (R/W) 64 00
DPLL2_frequency
cnfg_DPLL1_frequency (R/W) 65 01
APLL2_for_
DPLL1_E1/
DS1
DPLL1_freq_to_APLL2
DPLL1_frequency
cnfg_DPLL2_bw (R/W)
66 00
DPLL2_bandwidth
cnfg_DPLL1_locked_bw (R/W) 67 10
DPLL1_locked_bandwidth
cnfg_DPLL1_acq_bw (R/W)
69 11
DPLL1_acquisition_bandwidth
cnfg_DPLL2_damping (R/W)
6A 13
DPLL2_PD2_gain_alog
DPLL2_damping
cnfg_DPLL1_damping (R/W)
6B 14
DPLL1_PD2_gain_alog_8k
DPLL1_damping
cnfg_DPLL2_PD2_gain (R/W)
6C C2 DPLL2_PD2_
gain_enable
DPLL2_PD2_gain_digital
cnfg_DPLL1_PD2_gain (R/W)
6D C2 DPLL1_PD2_
gain_enable
DPLL1_PD2_gain_alog
DPLL1_PD2_gain_digital
cnfg_phase_loss_fine_limit (R/W) 73 A2 fine_limit_en noact_ph_loss narrow_en
phase_loss_fine_limit
cnfg_phase_loss_coarse_limit
(R/W)
74 E5 coarse_lim_ wide_range_ multi_ph_resp
phaseloss_en en
phase_loss_coarse_limit
cnfg_ip_noise_window (R/W)
76 06 ip_noise_
window_en
cnfg_sync_pulses (R/W)
7A 00 2k_8k_from_
DPLL2
8k_invert
8k_pulse
2k_invert
2k_pulse
cnfg_LOS_alarm (R/W)
7D 02
LOS_GPO_en LOS_tristate_ LOS_
en
polarity
cnfg_protection (R/W)
7E 85
protection_value
Revision 4.01/June 2006 © Semtech Corp.
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