ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 34
Register Name cnfg_input_mode
FINAL
DATASHEET
Description
(R/W) Register controlling various Default Value 1100 0010*
input modes of the device.
Bit 7
Bit 6
Bit 5
XO_edge
Bit 4
Bit 3
Bit 2
ip_sonsdhb
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:6]
5
[4:3]
2
[1:0]
Not used.
XO_edge
If the 12.8 MHz oscillator module connected to
REFCLK has one edge faster than the other, then for
jitter performance reasons, the faster edge should
be selected. This bit allows either the rising edge or
the falling edge to be selected.
Not used.
ip_sonsdhb
Bit to configure input frequencies to be either
SONET or SDH derived. This applies only to
selections of 0001 (bin) in the
cnfg_ref_source_frequency registers when the
input frequency is either 1544 kHz or 2048 kHz.
*The default value of Bit 2 is taken from the value
of the SONSDHB pin at power-up.
Not used.
-
-
0
Device uses the rising edge of the external
oscillator.
1
Device uses the falling edge of the external
oscillator.
-
-
0
SDH- inputs set to 0001 expected to be 2048 kHz.
1
SONET- inputs set to 0001 expected to be
1544 kHz.
-
-
Address (hex): 35
Register Name cnfg_DPLL2_path
Description
Bit 7
Bit No.
7
6
[5:0]
Bit 6
DPLL2_dig_
feedback
Bit 5
Bit 4
Description
Not used.
DPLL2_dig_feedback
Bit to select digital feedback mode for DPLL2.
Not used.
(R/W) Register to configure the Default Value 0100 0000
feedback mode of DPLL2.
Bit 3
Bit 2
Bit 1
Bit 0
Bit Value Value Description
-
-
0
DPLL2 in analog feedback mode.
1
DPLL2 in digital feedback mode.
-
-
Revision 4.01/June 2006 © Semtech Corp.
Page 37
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