ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 22
Register Name cnfg_ref_source_frequency
SEC1
FINAL
Description
(R/W) Configuration of the
frequency and input monitoring
for input SEC<n>. For Reg. 22,
<n> = 1.
DATASHEET
Default Value 0000 XXXX
Where XXXX is set by values on
Pins IP_FREQ[2:0] and SONSDHB
See Note in Description [3:0].
Bit 7
divn_SEC<n>
Bit 6
lock8k_SEC<n>
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
reference_source_frequency_SEC<n>
Bit 0
Bit No.
Description
Bit Value Value Description
7
6
[5:4]
[3:0]
divn_SEC<n>
This bit selects whether or not input SEC<n> is
divided in the programmable pre-divider prior to
being input to the DPLL and frequency monitor- see
Reg. 46 and Reg. 47 (cnfg_freq_divn).
lock8k_SEC<n>
This bit selects whether or not input SEC<n> is
divided in the preset pre-divider prior to being input
to the DPLL. This results in the DPLL locking to the
reference after it has been divided to 8 kHz. This bit
is ignored when divn_SEC<n> is set (bit = 1).
Not used.
reference_source_frequency_SEC<n>
Programs the frequency of the SEC connected to
input SEC<n>. If divn_SEC<n> is set then this value
should be set to 0000 (8 kHz).
Note...The value on the pins IP_FREQ [2:0] and
SONSDHB determines the default expected input
frequency which, at power-up/reset is written to
both cnfg_ref_source_frequency registers, giving
each the same default value. The values in each
register can, after the initialization period (251 ms
after PORB goes High), be changed on an individual
basis by writing to each register separately via the
serial interface, however any subsequent reset will
cause these registers’ values to be overwritten by
whatever value is on the pins at the time of the
reset. See “Preconfiguring Inputs - Expected Input
Frequency” and Table 4 on page 7.
0
Input SEC<n> fed directly to DPLL and monitor.
1
Input SEC<n> fed to DPLL and monitor via pre-
divider.
0
Input SEC<n> fed directly to DPLL.
1
Input SEC<n> fed to DPLL via preset pre-divider.
-
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
-
8 kHz.
1544/2048 kHz (dependant on Bit 2 (ip_sonsdhb)
in Reg. 34).
6.48 MHz.
19.44 MHz.
25.92 MHz.
38.88 MHz.
51.84 MHz.
77.76 MHz.
Not used.
2 kHz.
4 kHz.
Not used.
Address (hex): 23
cnfg_ref_source_frequency SEC2
As Reg. 22, but for SEC2, i.e. <n> = 2 Default = 0000 0000
Revision 4.01/June 2006 © Semtech Corp.
Page 36
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