ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 41
Register Name cnfg_DPLL_freq_limit
[7:0]
FINAL
Description
(R/W) Bits [7:0] of the DPLL
frequency limit register.
DATASHEET
Default Value 1111 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits[7:0] of cnfg_DPLL_freq_limit
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:0]
Bits [7:0] of cnfg_DPLL_freq_limit
This register defines the extent of frequency offset
to which DPLL1 will track a source before limiting-
i.e. it represents the pull-in range of the DPLLs. The
offset of the device is determined by the frequency
offset of the DPLL when compared to the offset of
the external crystal oscillator clocking the device. If
the oscillator is calibrated using
cnfg_nominal_frequency Reg. 3C and 3D, then this
calibration is automatically taken into account. The
DPLL frequency limit limits the offset of the DPLL
when compared to the calibrated oscillator
frequency.
-
In order to calculate the frequency limit in ppm,
Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need
to be concatenated. This value is a unsigned integer
and represents limit both positive and negative in
ppm. The value multiplied by 0.078 will give the
value in ppm.
Address (hex): 42
Register Name cnfg_DPLL_freq_limit
[9:8]
Bit 7
Bit 6
Bit 5
Description
Bit 4
Bit No.
[7:2]
[1:0]
Description
Not used.
Bits [9:8] of cnfg_DPLL_freq_limit.
(R/W) Bits [9:8] of the DPLL
frequency limit register.
Default Value 0000 0011
Bit 3
Bit 2
Bit 1
Bit 0
Bits [9:8] of cnfg_DPLL_freq_limit
Bit Value Value Description
-
-
-
See Reg. 41 (cnfg_DPLL_freq_limit) for details.
Revision 4.01/June 2006 © Semtech Corp.
Page 41
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