ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 46
Register Name cnfg_freq_divn
[7:0].
FINAL
Description
(R/W) Bits [7:0] of the division
factor for inputs using the DivN
feature.
DATASHEET
Default Value 1111 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
divn_value [7:0] (divide input frequency by n)
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:0]
divn_value[7:0].
-
See Reg. 47 (cnfg_freq_divn {13:8]) for details.
Address (hex): 47
Register Name cnfg_freq_divn
[13:8]
Description
(R/W) Bits [13:8] of the division
factor for inputs using the DivN
feature.
Default Value
0011 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
divn_value [13:8] (divide input frequency by n)
Bit 0
Bit No.
Description
Bit Value Value Description
[7:6]
[5:0]
Not used.
divn_value[13:8]
This register, in conjunction with Reg. 46
(cnfg_freq_divn) represents the integer value by
which to divide inputs that use the DivN pre-divider.
The DivN feature supports input frequencies up to a
maximum of 100 MHz; therefore, the maximum
value that should be written to this register is 30D3
hex (12499 dec). Use of higher DivN values may
result in unreliable behavior.
-
-
-
The input frequency will be divided by the value in
this register plus 1. i.e. to divide by 8, program a
value of 7.
Address (hex): 4B
Register Name cnfg_registers_source_select
Bit 7
Bit 6
Bit 5
Bit No.
[7:5]
Description
Not used.
Description
(R/W) Register to select the
Default Value 0000 0000
source of many of the registers.
Bit 4
DPLL1_DPLL2_
select
Bit 3
Bit 2
Bit 1
Bit 0
Bit Value Value Description
-
-
Revision 4.01/June 2006 © Semtech Corp.
Page 42
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