ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 63 (cont...)
Register Name cnfg_output_frequency
(MFrSync/FrSync)
FINAL
DATASHEET
Description
(R/W) Register to configure and Default Value
enable the frequencies available
on outputs MFrSync and FrSync.
1100 0000
Bit 7
MFrSync_en
Bit 6
FrSync_en
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
6
[5:0]
FrSync_en
Register bit to enable the 8 kHz Sync output
(FrSync).
Not used.
0
Output FrSync disabled.
1
Output FrSync enabled.
-
-
Address (hex): 64
Register Name cnfg_DPLL2_frequency
Description
(R/W) Register to configure
DPLL2 Frequency
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DPLL2_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
[7:4]
[2:0]
Not used.
DPLL2_frequency
Register to configure the frequency of operation of
DPLL2. The frequency of DPLL2 will also affect the
frequency of the APLL2 which, in turn, affects the
frequencies available at outputs O1 and O2 see
Reg. 61 and Reg. 62. It is also possible to not use
DPLL2 at all, but use the APLL2 to run directly from
DPLL1 output, see Reg. 65
(cnfg_DPLL1_frequency). If any frequencies are
required from the APLL2 then DPLL2 should not be
squelched, as the APLL2 input is squelched and the
APLL2 will free run.
-
-
000
DPLL2 squelched (clock off).
001
77.76 MHz (OC-N rates),
APLL2 frequency = 311.04 MHz.
010
12E1, APLL2 frequency = 98.304 MHz.
011
16E1, APLL2 frequency = 131.072 MHz.
100
24DS1, APLL2 frequency = 148.224 MHz.
101
16DS1, APLL2 frequency = 98.816 MHz.
110
E3, APLL2 frequency = 274.944 MHz.
111
DS3, APLL2 frequency = 178.944 MHz.
Revision 4.01/June 2006 © Semtech Corp.
Page 48
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