AD9851-CGPCB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9851-CGPCB' PDF : 24 Pages View PDF
AD9851
Parameter
Temp
Test
Level
AD9851BRS
Min Typ Max
Unit
TIMING CHARACTERISTICS4
tWH, tWL (W_CLK Min Pulse Width High/Low)
Full
IV
tDS, tDH (Data to W_CLK Setup and Hold Times)
Full
IV
tFH, tFL (FQ_UD Min Pulse Width High/Low)
Full
IV
tCD (REFCLK Delay After FQ_UD)5
Full
IV
tFD (FQ_UD Min Delay After W_CLK)
Full
IV
tCF (Output Latency from FQ_UD)
Frequency Change
Full
IV
Phase Change
Full
IV
tRH (CLKIN Delay After RESET Rising Edge)
tRL (RESET Falling Edge After CLKIN)
tRR (Recovery from RESET)
tRS (Minimum RESET Width)
tOL (RESET Output Latency)
Wake-Up Time from Power-Down Mode6
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
25°C
V
3.5
3.5
7
3.5
7
18
13
3.5
3.5
2
5
13
5
ns
ns
ns
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
µs
CMOS LOGIC INPUTS
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 1 Voltage, 2.7 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Rise/Fall Time
Input Capacitance
25°C
I
25°C
IV
25°C
IV
25°C
IV
25°C
I
25°C
I
25°C
IV
25°C
V
3.5
V
2.4
V
2.0
V
0.8
V
12
µA
12
µA
100
ns
3
pF
POWER SUPPLY
VS6 Current @:
62.5 MHz Clock, 2.7 V Supply
100 MHz Clock, 2.7 V Supply
62.5 MHz Clock, 3.3 V Supply
125 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
180 MHz Clock, 5 V Supply
Power Dissipation @ :
62.5 MHz Clock, 5 V Supply
62.5 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 2.7 V Supply
100 MHz Clock, 2.7 V Supply
125 MHz Clock, 5 V Supply
125 MHz Clock, 3.3 V Supply
180 MHz Clock, 5 V Supply
PDISS Power-Down Mode @:
5 V Supply
2.7 V Supply
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
25°C
VI
30
35
mA
40
50
mA
35
45
mA
55
70
mA
50
65
mA
70
90
mA
110
130
mA
250
325
mW
115
150
mW
85
95
mW
110
135
mW
365
450
mW
180
230
mW
555
650
mW
17
55
mW
4
20
mW
NOTES
1+VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD. Voltages applied to these pins should be of the same potential.
2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when the
clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
3The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur’s,
noise), slower slew rate, and low comparator overdrive.
4Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-
ence clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the external reference clock to
ensure proper timing.
5Not applicable when 6 REFCLK Multiplier is engaged.
6Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
REV. D
–3–
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