AD9851-CGPCB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9851-CGPCB' PDF : 24 Pages View PDF
AD9851
–120
–125
AD9851 RESIDUAL PHASE NOISE
–130
–135
–140
–145
–150
–155
100
1k
10k
FREQUENCY OFFSET – Hz
100k
TPC 11. Output Residual Phase Noise (5.2 MHz AOUT), 6
REFCLK Multiplier Disabled, System Clock = 180 MHz, Ref-
erence Clock = 180 MHz
75
70
FUNDAMENTAL OUTPUT =
SYSTEM CLOCK/3
65
60
VS = +3.3V
55
VS = +5V
50
45
10 20 40 60 80 100 120 140 160 180
SYSTEM CLOCK FREQUENCY – MHz
TPC 12. Spurious-free dynamic range (SFDR) is generally
a function of the DAC analog output frequency. Analog
output frequencies of 1/3 the system clock rate are consid-
ered worst case. Plotted below are typical worst case SFDR
numbers for various system clock rates.
Tek Stop 2.50GS/s
22 Acgs
T[]
: 2.0ns
@ : 105.2ns
C1 Rise
2.03ns
1
Ch1 100mV
M 20.0ns Ch 1 252mV
D 5.00ns Runs After
TPC 13. Comparator Rise Time, 15 pF Load
–8–
Tek Stop 2.50GS/s
2227 Acgs
T[ ]
: 2.3ns
@ : 103.6ns
C1 Fall
2.33ns
1
Ch1 100mV
M 20.0ns Ch 1 252mV
D 5.00ns Runs After
TPC 14. Comparator Fall Time, 15 pF Load
120
110
100
90
80
70
60
50
40
30
0
VS = +5V
VS = +3.3V
10
20
30
40
50
60
70
ANALOG OUTPUT FREQUENCY – MHz
TPC 15. Supply current variation with analog
output frequency at 180 MHz system clock (upper
trace) and 125 MHz system clock (lower trace)
120
100
80
VS = +5V
60
40
VS = +3.3V
20
0
0 20 40 60 80 100 120 140 160 180
SYSTEM CLOCK – MHz
TPC 16. Supply current variation with system
clock frequency
REV. D
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