AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
DELAYED SYNC-IN SIGNAL
SYNC_IN
LVDS
RECEIVER
7
8
SYNC
RECEIVER
DELAY
5
PROGAMMABLE
DELAY
SYNC_SMP_ERR 12
SETUP AND HOLD
VALIDATION
SYNC STATE
PRESET VALUE
SYNC
RECEIVER
ENABLE
6
D1 Q1
D2 Q2
D3 Q3
D4 Q4
RISING EDGE
DETECTOR
D5 Q5
D6 Q6
AND
STROBE
LOAD
GENERATOR
CLOCK
GENERATOR
CLOCK
STATE
INTERNAL
CLOCKS
SYSCLK
SYNC
TIMING
VALIDATION
DISABLE
4
SYNC
VALIDATION
DELAY
SYNC PULSE
Figure 51. Sync Receiver Diagram
EDGE
ALIGNED
AT REF_CLK
INPUTS.
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
CLOCK
SOURCE
FPGA
DATA
REF_CLK
AD9910
NUMBER 1
SYNC SYNC
IN OUT
MASTER DEVICE
FPGA
FPGA
DATA
REF_CLK
AD9910
NUMBER 2
SYNC SYNC
IN OUT
DATA
REF_CLK
AD9910
NUMBER 3
SYNC SYNC
IN OUT
EDGE
ALIGNED
AT SYN_IN
INPUTS.
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
Figure 52. Multichip Synchronization Example
The sync receiver accepts a periodic clock signal at the
SYNC_IN pins. This signal is assumed to originate from an
LVDS-compatible driver. The user can delay the SYNC_IN
signal in steps of ~150 ps by programming the 5-bit sync
receiver delay word in the multichip sync register. For the sake
of discussion, the signal at the output of the programmable
delay is referred to as the delayed sync-in signal.
The edge detection logic generates a sync pulse having a dura-
tion of one SYSCLK cycle with a repetition rate equal to the
frequency of the signal applied to the SYNC_IN pins. The sync
pulse is generated as a result of sampling the rising edge of the
delayed sync-in signal with the rising edge of the local SYSCLK.
The sync pulse is routed to the internal clock generator, which
behaves as a presettable counter clocked at the SYSCLK rate.
The sync pulse presets the counter to a predefined state
(programmable via the 6-bit sync state preset value word in the
multichip sync register). The predefined state is only active for a
single SYSCLK cycle, after which the clock generator resumes
cycling through its state sequence at the SYSCLK rate. This
unique state presetting mechanism gives the user the flexibility
to synchronize devices with specific relative clock state offsets
(by assigning a different sync state preset value word to each
device).
Multiple device synchronization is accomplished by providing
each AD9910 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is, they
Rev. 0 | Page 44 of 60
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