AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
communication cycle can begin, starting with the instruction
byte write.
I/O_UPDATE—Input/Output Update
The I/O_UPDATE initiates the transfer of written data from
the I/O port buffer to active registers. I/O_UPDATE is active
on the rising edge and its pulse width must be greater than one
SYNC_CLK period. It is either an input or output pin depending
on the programming of the Internal I/O update active bit.
SERIAL I/O TIMING DIAGRAMS
The diagrams below provide basic examples of the timing
relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
AD9910
MSB/LSB TRANSFERS
The AD9910 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in Control Function
Register 1 (0x00). The default format is MSB first. If Bit 0 is set
high, the serial port is configured for LSB-first format. If LSB
first is active, all data, including the instruction byte, must
follow LSB-first convention. Note that the highest number
found in the bit range column for each register (see the Register
Map and Bit Descriptions section and Table 16) is the MSB and
the lowest number is the LSB for that register.
CS
SCLK
SDIO
I7
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I6
I5 I4
I3
I2
I1
I0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. Serial Port Write Timing, Clock Stall Low
CS
SCLK
SDIO
I7
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
DO7 DO6 DO5 DO4 DO3 DO2 DO1
DO0
Figure 55. 3-Wire Serial Port Read Timing, Clock Stall Low
CS
SCLK
SDIO
CS
SCLK
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I7 I6 I5 I4 I3 I2 I1 I0
D7
D6 D5 D4 D3 D2 D1
D0
Figure 56. Serial Port Write Timing, Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I7
I6
I5
I4
I3
I2
I1
I0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Figure 57. 2-Wire Serial Port Read Timing, Clock Stall High
Rev. 0 | Page 47 of 60
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