AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
REGISTER MAP AND BIT DESCRIPTIONS
Table 16. Register Map
Register
Name
(Serial
Address)
Bit Range
(Internal
Address)
CFR1—
Control
Function
Register 1
(0x00)
31:24
23:16
15:8
7:0
CFR2—
Control
Function
Register 2
(0x01)
31:24
23:16
15:8
7:0
CFR3—
Control
Function
Register 3
(0x02)
31:24
23:16
15:8
Auxiliary
DAC
Control
(0x03)
I/O Update
Rate (0x04)
FTW—
Frequency
Tuning
Word
(0x07)
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RAM
Enable
RAM Playback
Destination
Open
Manual
OSK
External
Control
Inverse
Sinc Filter
Enable
Open
Internal Profile Control
Select DDS
Sine Output
Load LRR
@ I/O
Update
Autoclear
Digital
Ramp
Accum.
Autoclear
Phase
Accum.
Clear
Digital
Ramp
Accum.
Clear
Phase
Accum.
Load ARR
@ I/O
Update
OSK
Enable
Select Auto
OSK
Digital
Power-
Down
DAC
Power-
Down
REFCLK
Input
Power-
Down
Aux DAC
Power-
Down
External
Power-
Down
Control
Open
SDIO
LSB First
Input Only
Open
DROVER
Pin Active
Enable
Amplitude
Scale from
Single Tone
Profiles
Internal
I/O
Update
Active
SYNC_CLK
Enable
Digital Ramp
Destination
Digital
Ramp
Enable
Digital
Ramp
No-Dwell
High
Digital
Ramp
No-Dwell
Low
Read
Effective
FTW
I/O Update Rate Control
Open
PDCLK
Enable
PDCLK
Invert
TxEnable
Invert
Open
Matched
Latency
Enable
Data
Assembler
Hold Last
Value
Sync
Sample
Error Mask
Parallel
Data Port
Enable
FM Gain
DRV0<1:0>
Open<5:3>
VCO SEL<2:0>
Open
ICP<2:0>
Open
REFCLK
Input
Divider
Bypass
REFCLK
Input
Divider
ResetB
Open
PLL Enable
N<6:0>
Open
Open
Open
Open
FSC<7:0>
I/O Update Rate<31:24>
I/O Update Rate<23:16>
I/O Update Rate<15:8>
I/O Update Rate<7:0>
Frequency Tuning Word<31:24>
Frequency Tuning Word<23:16>
Frequency Tuning Word<15:8>
Frequency Tuning Word<7:0>
Default
Value5
(Hex)
0x00
0x00
0x00
0x00
0x00
0x40
0x08
0x20
0x1F
0x3F
0x40
0x00
0x00
0x00
0x7F
0x7F
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
Rev. 0 | Page 48 of 60
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