ADJD-S312-CR999 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ADJD-S312-CR999' PDF : 18 Pages View PDF
Powering the Device
Ground Connection
AGND and DGND must both be set to 0V and preferably
star-connected to a central power source as shown in
the application diagram. A potential difference between
AGND and DGND may cause the ESD diodes to turn on
inadvertently.
Application Diagrams
HOST
SYSTEM
A4 SLEEP
DVDD
XRST
SDA
SCL
HOST
SYSTEM
D4
XRST
C4
SDASLV
C3
SCLSLV
AVDD
A1
AGND
A2, A3,
D2
Voltage
Regulator
DGND DVDD
C2
D1
Voltage
Regulator
Star-connected ground
Pin Information
Pin Name Type
Description
A1 AVDD Power
Analog power pin.
A2 AGND Ground
Tie to analog ground.
A3 AGND Ground
Tie to analog ground.
A4 SLEEP Input
When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog circuits are
powered down and the clock signal is gated away from the core logic resulting in very
low current consumption.
B1 NC
No connect
No connect. Leave floating.
B2 NC
No connect
No connect. Leave floating.
B3 NC
No connect
No connect. Leave floating.
B4 NC
No connect
No connect. Leave floating.
C1 NC
No connect
No connect. Leave floating
C2 DGND Ground
Tie to digital ground.
C3 SCLSLV Input
SDASLV and SCLSLV are the serial interface communications pins. SDASLV is the bidi-
C4
SDASLV
Input/
Output(tri-state
rectional data pin and SCLSLV is the interface clock. A pull-up resistor should be tied to
SDASLV because it goes tri-state to output logic 1.
high)
D1 DVDD Power
Digital power pin.
D2 AGND Ground
Tie to analog ground.
D3 NC
No connect
No connect. Leave floating.
D4 XRST Input
Global, asynchronous, active-low system reset. When asserted low, XRST resets all regis-
ters. Minimum reset pulse low is 1 us and must be provided by external circuitry.
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