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ADNS-2610 View Datasheet(PDF) - Avago Technologies

Part Name
Description
MFG CO.
ADNS-2610
AVAGO
Avago Technologies AVAGO
'ADNS-2610' PDF : 27 Pages View PDF
Read Operation
A read operation, meaning data that is going from the
ADNS-2610 to the microcontroller, is always initiated by
the microcontroller and consists of two bytes. The first
byte that contains the address is written by the microcon-
troller and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-2610. The transfer is synchronized by SCK. SDIO is
changed on falling edges of SCK and read on every rising
edge of SCK. The microcontroller must go to a High-Z
state after the last address data bit. The ADNS-2610 will
go to the High-Z state after the last data bit. Another
thing to note during a read operation; SCK needs to be
delayed after the last address data bit to ensure that the
ADNS-2610 has at least 100 µs to prepare the requested
data. This is shown in the timing diagrams below (See
Figures 21 to 23).
SCK
Cycle #
SCK
SDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21. Read operation.
SDIO Driven by Microcontroller
Detail "A"
Detail "A"
SCK
Microcontroller
to ADNS-2610
SDIO handoff
SDIO
A1
t HOLD
100 µs, min
60 ns, min
0 ns, min
A0
250 ns, min
Figure 22. Microcontroller to ADNS-2610 SDIO handoff.
SDIO Driven by ADNS-2610
250 ns, max
Detail "B"
Hi-Z
D7
250 ns, max
D6
160 ns, min
Detail "B"
SCK
ADNS-2610 to
Microcontroller
SDIO handoff
SDIO
D0
250 ns, min
160 ns, max
R/W bit of next address
Released by ADNS-2610
Driven by microcontroller
Figure 23. ADNS-2610 to microcontroller SDIO handoff.
NOTE:
The 250 ns high state of SCK is the minimum data hold time of the ADNS-
2610. Since the falling edge of SCK is actually the start of the next read
or write command, the ADNS-2610 will hold the state of D0 on the SDIO
line until the falling edge of SCK. In both write and read operations, SCK
is driven by the microcontroller.
13
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