ADNS-2610 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ADNS-2610' PDF : 27 Pages View PDF
Required Timing between Read and Write Commands
(tsxx)
There are minimum timing requirements between read
and write commands on the serial port.
SCK
Address
Data
Write Operation
Figure 25. Timing between two write commands.
t SWW
≥100 µs
Address
Data
Write Operation
If the rising edge of the SCK for the last data bit of the
second write command occurs before the 100 microsec-
ond required delay, then the first write command may
not complete correctly.
SCK
Address
Data
Write Operation
Figure 26. Timing between write and read commands.
t SWR
≥100 µs
If the rising edge of SCK for the last address bit of the read
command occurs before the 100 microsecond required de-
lay, then the write command may not complete correctly.
Address
Next Read
Operation
SCK
Address
t1
≥100 µs
Read Operation
Figure 27. Timing between read and either write or subsequent read commands.
tSRW and tSRR
>250 ns
Data
Address
Next Read or
Write Operation
The falling edge of SCK for the first address bit of either
the read or write command must be at least 250 ns after
the last SCK rising edge of the last data bit of the previous
read operation.
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