ADNS-2610 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ADNS-2610' PDF : 27 Pages View PDF
Forcing the SDIO Line to the Hi-Z State
There are times when the SDIO line from the ADNS-2610
should be in the Hi-Z state. For example, if the micropro-
cessor has completed a write to the ADNS-2610, the SDIO
line will go into a Hi-Z state, because the SDIO pin was
configured as an input. However, if the last operation from
the microprocessor was a read, the ADNS-2610 will hold
the D0 state on SDIO until a falling edge of SCK.
PD
Timing
PD
Activated
32
clock
cycles
SDIO
10 ns, max
Hi-Z
To place the SDIO pin into a Hi-Z state, activate the power-
down mode by writing to the configuration register.
Then, the power-down mode can stay activated, with the
ADNS-2610 in the shutdown state, or the power-down
mode can be deactivated, returning the ADNS-2610 to
normal operation. In both conditions, the SDIO line will
go into the Hi-Z state.
Figure 24. SDIO Hi-z state and timing.
14
Share Link: 
