ADSP-21362WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21362WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 30. IDP
signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 30. IDP
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
3
ns
tSIHFS1
FS Hold After SCLK Rising Edge
3
ns
tSISD1
SDATA Setup Before SCLK Rising Edge
3
ns
tSIHD1
SDATA Hold After SCLK Rising Edge
3
ns
tIDPCLKW
Clock Width
9
ns
tIDPCLK
Clock Period
24
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tIDPCLKW
SAMPLE EDGE
tIDPCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 24. IDP Master Timing
Rev. A | Page 34 of 52 | December 2006
Share Link: 
