ADSP-21362WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21362WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Pulse-Width Modulation Generators
Table 32. PWM Timing
Parameter
Switching Characteristics
tPWMW
tPWMP
PWM Output Pulse Width
PWM Output Period
Min
tPCLK – 2
2 × tPCLK – 1.5
Max
(216 – 2) × tPCLK – 2
(216 – 1) × tPCLK
Unit
ns
ns
PWM
OUTPUTS
tPWMW
tP W MP
Figure 26. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in Table 33 are valid at the DAI_P20–1 pins.
This feature is not available on the ADSP-21363 models.
Table 33. SRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
FS Setup Before SCLK Rising Edge
3
ns
tSRCHFS1
FS Hold After SCLK Rising Edge
3
ns
tSRCSD1
SDATA Setup Before SCLK Rising Edge
3
ns
tSRCHD1
SDATA Hold After SCLK Rising Edge
3
ns
tSRCCLKW
Clock Width
36
ns
tSRCCLK
Clock Period
80
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tSRCCLKW
SAMPLE EDGE
tSRCCLK
tSRCSFS
tSRCHFS
tSRCSD
tSRCHD
Figure 27. SRC Serial Input Port Timing
Rev. A | Page 36 of 52 | December 2006
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