ADSP-21362WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21362WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPDIF Receiver
The following section describes timing as it relates to the SPDIF
receiver. This feature is not available on the
ADSP-21363 models.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode)
Parameter
Switching Characteristics
tDFSI
LRCLK Delay After SCLK
tHOFSI
LRCLK Hold After SCLK
tDDTI
Transmit Data Delay After SCLK
tHDTI
tSCLKIW1
Transmit Data Hold After SCLK
Transmit SCLK Width
tCCLK
Core Clock Period
1 SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
Min
Max
Unit
5
ns
–2
ns
5
ns
–2
ns
38
ns
5
ns
DRIVE EDGE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
tHOFSI
tHDTI
tDFSI
tSCLKIW
tDDTI
SAMPLE EDGE
Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing
Rev. A | Page 40 of 52 | December 2006
Share Link: 
