ADSP-21362WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21362WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 31. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor
Hardware Reference. Note that the most significant 16 bits of
external PDAP data can be provided through either the parallel
port AD15–0 or the DAI_P20–5 pins. The remaining 4 bits can
only be sourced through DAI_P4–1. The timing below is valid
at the DAI_P20–1 pins or at the AD15–0 pins.
Table 31. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
tSPCLKEN1
tHPCLKEN1
tPDSD1
tPDHD1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
tPDCLKW
Clock Width
tPDCLK
Clock Period
Min
Max
Unit
2.5
ns
2.5
ns
3.0
ns
2.5
ns
7.0
ns
24
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
2 × tPCLK – 1
ns
tPDSTRB
PDAP Strobe Pulse Width
2 × tPCLK – 1.5
ns
1 Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
DAI_P20-1
(PDAP_CLK)
DAI_P20-1
(PDAP_CLKEN)
DATA
SAMPLE EDGE
tPDCLKW
tPDCLK
tSPCLKEN
tPDSD
tHPCLKEN
tPDHD
DAI_P20-1
(PDAP_STROBE)
tPDHLDD
Figure 25. PDAP Timing
tPDSTRB
Rev. A | Page 35 of 52 | December 2006
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