ADSP-21365/6
Preliminary Technical Data
MAXIMUM POWER DISSIPATION
The data in this table is based on theta JA (θJA) established per
JEDEC standards JESD51-2 and JESD51-6. See Engineer-to-
Engineer note (EE-TBD) for further information. For informa-
tion on package thermal specifications, see Thermal
Characteristics on page 44.
Max Ambient 144 INT–HS 144 INT–HS 136 Mini- 136 Mini-
Temp1
LQFP2
LQFP3
BGA4
BGA5
70°C
3.33W
2.10W
2.44W
2.18W
85°C
2.42W
N/A
1.77W
N/A
105°C
1.21W
N/A
N/A
N/A
1 Power Dissipation greater than that listed above may cause permanent damage to the device.
For more information, see Thermal Characteristics on page 44.
2 Heat slug soldered to PCB
3 Heat slug not soldered to PCB
4 Thermal vias in PCB
5 No thermal vias in PCB
ABSOLUTE MAXIMUM RATINGS
Parameter
Internal (Core) Supply Voltage (VDDINT)1
Analog (PLL) Supply Voltage (AVDD)1
External (I/O) Supply Voltage (VDDEXT)1
Input Voltage–0.5 V to VDDEXT1
Output Voltage Swing–0.5 V to VDDEXT1
Load Capacitance1
Storage Temperature Range1
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+ 0.5 V
+ 0.5 V
200 pF
–65°C to +150°C
Junction Temperature under Bias
125°C
1 Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21365/6 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
The ADSP-21365/6’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see Table 7 on page 14). To determine switching frequencies
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the serial
ports).
The ADSP-21365/6’s internal clock switches at higher frequen-
cies than the system input clock (CLKIN). To generate the
internal clock, the processor uses an internal phase-locked loop
Rev. PrA | Page 16 of 54 | September 2004