ADSP-21365SBBC-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21365SBBC-ENG' PDF : 54 Pages View PDF
ADSP-21365/6
Preliminary Technical Data
Reset
Table 12. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST1
RESET Pulse Width Low
4tCK
ns
tSRST
RESET Setup Before CLKIN Low
8
ns
1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
tWRST
Figure 9. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 13. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
tSRST
Min
2 × tPCLK +2
Max
DAI_P20-1
FLAG2-0
(IRQ2-0)
tIPW
Figure 10. Interrupts
Unit
ns
Rev. PrA | Page 20 of 54 | September 2004
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