ADSP-21365SBBC-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21365SBBC-ENG' PDF : 54 Pages View PDF
Preliminary Technical Data
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the processor’s internal
clock (the clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (Table 8).
Table 8. ADSP-21365/6 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description Calculation
Input Clock
Core Clock
1/tCK
1/tCCLK
Table 9. Clock Periods
Timing
Requirements
Description1
tCK
CLKIN Clock Period
tCCLK
(Processor) Core Clock Period
tPCLK
(Peripheral) Clock Period = 2 × tCCLK
tSCLK
Serial Port Clock Period = (tPCLK) × SR
tSPICLK
SPI Clock Period = (tPCLK) × SPIR
1 where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
Figure 5 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.
CLKIN
XTAL
XTAL
OSC
PLLILCLK
PLL
6:1, 16:1,
32:1
CLKOUT
CCLK
(CORE CLOCK)
ADSP-21365/6
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on page 43 under Test Conditions for voltage refer-
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
CLK-CFG [1:0]
Figure 5. Core Clock and System Clock Relationship to CLKIN
Rev. PrA | Page 17 of 54 | September 2004
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