ADSP-21367 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21367' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 29. Serial Ports—External Clock
Parameter
Timing Requirements
t1
SFSE
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
t1
HFSE
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
t1
SDRE
Receive Data Setup Before Receive SCLK
t1
HDRE
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
t2
DFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
t2
HOFSE
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
t2
DDTE
Transmit Data Delay After Transmit SCLK
t2
HDTE
Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
10
ns
20
ns
10.25
ns
2
ns
9.6
ns
2
ns
Table 30. Serial Ports—Internal Clock
Parameter
Timing Requirements
t1
SFSI
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
t1
HFSI
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
t1
SDRI
Receive Data Setup Before SCLK
t1
HDRI
Receive Data Hold After SCLK
Switching Characteristics
t2
DFSI
t2
HOFSI
t2
DFSIR
t2
HOFSIR
t2
DDTI
t2
HDTI
t3
SCLKIW
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
1 Referenced to the sample edge.
2 Referenced to drive edge.
3 Minimum SPORT divisor register value.
Min
Max
Unit
7
ns
2.5
ns
7
ns
2.5
ns
–1.0
–1.0
–1.0
2 × tPCLK – 1.5
4
ns
ns
9.75
ns
ns
3.25
ns
ns
2 × tPCLK + 1.5 ns
Rev. C | Page 32 of 56 | January 2008
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