ADSP-21367/ADSP-21368/ADSP-21369
DAI_P20-1
(SCLK)
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
DAI_P20-1
(FS)
tHOFSIR
tDFSIR
tSFSI
DAI_P20-1
(DATA CHANNEL A/B)
tSDRI
tHFSI
tHDRI
DAI_P20-1
(SCLK)
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
tSCLKW
SAMPLE EDGE
DAI_P20-1
(FS)
tHOFSE
tDFSE
tSFSE
DAI_P20-1
(DATA CHANNEL A/B)
tSDRE
tHFSE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DAI_P20-1
(SCLK)
tSCLKIW
DAI_P20-1
(FS)
tHOFSI
tDFSI
tSFSI
tHDTI
DAI_P20-1
(DATA CHANNEL A/B)
tDDTI
tHFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DAI_P20-1
(SCLK)
tSCLKW
DAI_P20-1
(FS)
tHOFSE
tHDTE
DAI_P20-1
(DATA CHANNEL A/B)
tDFSE
tSFSE
tDDTE
tHFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DAI_P20-1
SCLK (EXT)
DRIVE EDGE
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE
tDDTEN
DAI_P20-1
SCLK (INT)
tDDTIN
DAI_P20-1
(DATA CHANNEL A/B)
Figure 23. Serial Ports
DRIVE EDGE
SCLK
tDDTTE
Rev. C | Page 34 of 56 | January 2008