ADSP-21367 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21367' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
Table 31. Serial Ports—Enable and Three-State
Parameter
Min
Switching Characteristics
t1
DDTEN
Data Enable from External Transmit SCLK
2
t1
DDTTE
Data Disable from External Transmit SCLK
t1
DDTIN
Data Enable from Internal Transmit SCLK
–1
1 Referenced to drive edge.
Table 32. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
t1
DDTLFSE
Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
t1
DDTENFS
Data Enable for MCE = 1, MFD = 0
0.5
1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Max
10
Max
7.75
Unit
ns
ns
ns
Unit
ns
ns
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
2ND BIT
tDDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
Figure 22. External Late Frame Sync1
1 This figure reflects changes made to support left-justified sample pair mode.
Rev. C | Page 33 of 56 | January 2008
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