ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 60 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read
Parameter
Min
Max
Unit
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid1
tSDS
Data Setup to RD High
2.5
tHDRH
Data Hold from RD High3, 4
0
tDAAK
ACK Delay from Address, Selects2, 5
tDSAK
ACK Delay from RD Low4
Switching Characteristics
W + tSDCLK – 5.12
ns
W – 3.2
ns
ns
ns
tSDCLK – 9.5 + W
ns
W – 7.0
ns
tDRHA
Address Selects Hold After RD High
RH + 0.20
ns
tDARL
Address Selects to RD Low2
tSDCLK – 3.3
ns
tRW
RD Pulse Width
W – 1.4
ns
tRWR
RD High to WR, RD Low
HI + tSDCLK – 0.8
ns
W = (number of wait states specified in AMICTLx register) × tSDCLK.
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK.
H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
1 Data delay/setup: system must meet tDAD, tDRLD, or tSDS.
2 The falling edge of MSx is referenced.
3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4 Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 46 for the calculation of hold times given capacitive and dc loads.
5 ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
ADDRESS
MSx
RD
DATA
ACK
tDARL
tRW
tDAAK
tDAD
tDRLD
tDSAK
tSDS
tDRHA
tHDRH
tRWR
WR
Figure 18. Memory Read
Rev. C | Page 28 of 56 | January 2008
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