ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 60 Pages View PDF
Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
ADSP-21367/ADSP-21368/ADSP-21369
Table 26. Memory Write
Parameter
Min
Max
Unit
Timing Requirements
tDAAK
ACK Delay from Address, Selects1, 2
tDSAK
ACK Delay from WR Low1, 3
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tDAWL
Address, Selects to WR Low2
tWW
WR Pulse Width
tDDWH
Data Setup Before WR High
tDWHA
Address Hold After WR Deasserted
tDWHD
Data Hold After WR Deasserted
tWWR
WR High to WR, RD Low
tDDWR
Data Disable Before RD Low
tWDE
WR Low to Data Enabled
W = (number of wait states specified in AMICTLx register) × tSDCLK.
H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
tSDCLK – 3.1 + W
tSDCLK – 2.7
W – 1.3
tSDCLK – 3.0 + W
H + 0.15
H + 0.02
tSDCLK – 1.5 + H
2tSDCLK – 4.11
tSDCLK – 3.5
tSDCLK – 9.7 + W
ns
W – 4.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
2 The falling edge of MSx is referenced.
3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
ADDRESS
MSx
WR
DATA
ACK
RD
tDAWL
tDAWH
tWW
tWDE
tDAAK
tDSAK
tDDWH
tDWHA
tWWR
tDDWR
tDWHD
Figure 19. Memory Write
Rev. C | Page 29 of 56 | January 2008
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