ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the specifications provided below are valid at the
DPI_P14–1 pins.
Table 19. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
2 × tPCLK – 2
DPI_P14–1
(TIMER1–0)
tPWMO
Figure 12. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the specifications provided below are valid at
the DPI_P14–1 pins.
Table 20. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
2 × tPCLK
DPI_P14–1
(TIMER1–0)
tPWI
Figure 13. Timer Width Capture Timing
ADSP-21371/ADSP-21375
Max
2 × (231 – 1) × tPCLK
Unit
ns
Max
2 × (231– 1) × tPCLK
Unit
ns
Rev. C | Page 23 of 52 | September 2009
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