ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 24. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
tHSDAT
DATA Hold After SDCLK
Switching Characteristics
tSDCLK
SDCLK Period
tSDCLKH
SDCLK Width High
tSDCLKL
tDCAD
tHCAD
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK2
Command, ADDR, Data Hold After SDCLK2
tDSDAT
Data Disable After SDCLK
tENSDAT
Data Enable After SDCLK
1 For FCCLK = 133 MHz (SDCLK ratio = 1:2).
2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
ADSP-21371/ADSP-21375
1.2 V, 266 MHz
Min
Max
Unit
0.58
ns
2.2
ns
7.5
ns
3
ns
3
ns
5.3
ns
1.3
ns
5.3
ns
1.6
ns
SDCLK
DATA (IN)
DATA (OUT)
CMND ADDR
(OUT)
tSSDAT
tSDCLK
tSDCLKH
tHSDAT
tSDCLKL
tENSDAT
tDCAD
tDSDAT
tHCAD
tDCAD
tHCAD
Figure 17. SDRAM Interface Timing for 133 MHz SDCLK
Rev. C | Page 27 of 52 | September 2009
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