ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tHFSE1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tSDRE1
tHDRE1
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tHOFSE2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tDDTE2
tHDTE2
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
1.2 V, 266 MHz
Min
Max
2.5
2.5
2.5
2.5
(tPCLK × 4) ÷ 2 – 0.5
tPCLK × 4
10.5
2
11
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 28. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tHFSI1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI2
tHOFSI2
tDFSIR2
tHOFSIR2
tDDTI2
tHDTI2
tSCKLIW3
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
1 Referenced to the sample edge.
2 Referenced to drive edge.
3 Minimum SPORT divisor register value.
1.2 V, 266 MHz
Min
Max
Unit
7
ns
2.5
ns
7
ns
2.5
ns
–1.0
–1.0
–1.0
0.5tPCLK – 2
4
ns
ns
10.7
ns
ns
3.6
ns
ns
0.5tPCLK + 2 ns
Rev. C | Page 30 of 52 | September 2009
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