ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
ADSP-21371/ADSP-21375
Table 26. Memory Write—Bus Master
1.2 V, 266 MHz
Parameter
Min
Max
Unit
Timing Requirements
tDAAK
ACK Delay from Address, Selects1, 2
tDSAK
ACK Delay from WR Low 1, 3
tSDCLK – 10.1 + W ns
W – 7.1
ns
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tSDCLK – 3.6 + W
ns
tDAWL
Address, Selects to WR Low2
tSDCLK – 2.7
ns
tWW
WR Pulse Width
W – 1.3
ns
tDDWH
Data Setup Before WR High
tSDCLK – 3.0 + W
ns
tDWHA
Address Hold After WR Deasserted
H + 0.15
ns
tDWHD
tDATRWH
Data Hold After WR Deasserted
Data Disable After WR Deasserted4
H + 0.02
ns
tSDCLK – 1.37 + H tSDCLK + 4.9 + H
ns
tWWR
WR High to WR, RD Low
tSDCLK – 1.5 + H
ns
tDDWR
Data Disable Before RD Low
2tSDCLK – 5.1
ns
tWDE
WR Low to Data Enabled
tSDCLK – 4.1
ns
W = (number of wait states specified in AMICTLx register) × tSDCLK, H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1 ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
2 The falling edge of MSx is referenced.
3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4 See Test Conditions on Page 45 for calculation of hold times given capacitive and dc loads.
ADDR
MSx
WR
DATA
ACK
RD
tDAWL
tWDE
tDAAK
tDSAK
tDAWH
tWW
tDDWH
Figure 19. Memory Write—Bus Master
tDWHA
tWWR
tDATRWH
tDDWR
tDWHD
Rev. C | Page 29 of 52 | September 2009
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