ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0)
tSSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
tDSOE
tDSDHI
tDDSPIDS
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
1.2 V, 266 MHz
Min
Max
4 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK
2 × tPCLK
2 × tPCLK
2
2
2 × tPCLK
0
0
2 × tPCLK
6.8
6.8
9.5
5 × tPCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
tSDSCO
tDSOE
MISO
(OUTPUT)
CPHASE = 1
MOSI
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tDDSPIDS
tSSPIDS
MSB
MSB VALID
MISO
(OUTPUT)
tDSOV
CPHASE = 0
MOSI
(INPUT)
MSB
tDDSPIDS
MSB VALID
tSPICLKS
tHDS
tDDSPIDS
LSB
tSSPIDS tHSPIDS
LSB VALID
tHDSPIDS
tSSPIDS
LSB
tHSPIDS
LSB VALID
Figure 31. SPI Slave Timing
tSDPPW
tDSDHI
tHDSPIDS
tDSDHI
Rev. C | Page 41 of 52 | September 2009
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