ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
TWI Controller Timing
Table 40 and Figure 33 provide timing information for the TWI
interface. Input signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1
Standard Mode
Parameter
Min
Max
fSCL
SCL Clock Frequency
0
100
tHDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
4.0
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
Low Period of the SCL Clock
4.7
High Period of the SCL Clock
4.0
Setup Time for a Repeated Start Condition
4.7
Data Hold Time for TWI-Bus Devices
0
Data Setup Time
250
Setup Time for Stop Condition
4.0
Bus Free Time Between a Stop and Start Condition 4.7
tSP
Pulse Width of Spikes Suppressed By the Input Filter n/a
n/a
1 All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 16.
Fast Mode
Min
Max
Unit
0
400
kHz
0.6
μs
1.3
μs
0.6
μs
0.6
μs
0
μs
100
ns
0.6
μs
1.3
μs
0
50
ns
DPI_P14–1
SDA
DPI_P14–1
SCL
S
tLOW
tSUDAT
tHDSTA
tHDSTA
tHDDAT
tHIGH
tSUSTA
Sr
tSP
tBUF
tSUSTO
P
S
Figure 33. Fast and Standard Mode Timing on the TWI Bus
Rev. C | Page 43 of 52 | September 2009
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