ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
DC SPECIFICATIONS– PCI Bus Pins
Parameter
Test Conditions
K Grade
Min
Max
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
CI
CCLK
CIDSEL
LPIN
Hi-Level Input Voltage1, 2
Lo-Level Input Voltage1, 2
Hi-Level Output Voltage1, 3
Lo-Level Output Voltage1, 3
Hi-Level Input Current2
Lo-Level Input Current2
Three-State Leakage Current4
Three-State Leakage Current1
Input Pin Capacitance
PCI CLK Pin Capacitance
PCI IDSEL Pin Capacitance5
Pin Inductance
IOUT = –500 µA
IOUT = 1500 µA
0 < VIN < VDD
0 < VIN < VDD
0 < VIN < VDD
0 < VIN < VDD
TAMB = 25°C
TAMB = 25°C
TAMB = 25°C
0.5 VDD
–0.5
0.9 VDD
5
VDD + 0.5
0.3 VDD
0.1 VDD
10
10
10
10
10
12
8
20
NOTES
1Bidirectional pins: MPLX_BUS [31:0}, MPLX1–4, MPLX7–10, MPLX12
2Input only pins: MPLX_RESET, MPLX5, MPLX6, PCI_CLK, PCI_PAR, PCI_IRDY, PCI_STOP
3Output only pins: MPLX11
4Leakage currents include High-Z output leakage for bidirectional buffers with three-state outputs.
5Lower capacitance of IDSEL (MPLX_5) input-only pin allows for nonresistive connection to Address/Data bus.
Unit
V
V
V
V
µA
µA
µA
µA
pF
pF
pF
nH
TIMING PARAMETERS
PCI Clock (Guaranteed Over Operating Temperature and Digital Supply Range)
The ADSP-2141L is targeted for use in PCI add-on I/O slave card designs. It provides a glueless interface to the PCI bus. All bus
drivers are compliant with PCI interface electrical switching and drive capability specifications.
The ADSP-2141L does not implement the following signals: LOCK, INTB, INTC, INTD, SBO, SDONE, CLKRUN, AD[64:32],
C/BE[7:4], REQ64, ACK64, PAR64.
Parameter
Min
Max
Unit
Timing Requirements:
tCYC
tHIGH
tLOW
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate1
RST Slew Rate2
25
100
ns
11
ns
11
ns
1
4
V/ns
50
mV/ns
NOTES
1Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the waveform as
shown in Figure 8.
2The minimum RST slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise cannot render an otherwise monotonic
signal to appear to bounce in the switching range.
0.6VCC
0.5VCC
0.4VCC
0.3VCC
0.2VCC
tHIGH
tCYC
tLOW
2V p-p
(MINIMUM)
Figure 8. Clock Waveform
–18–
REV. 0
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