ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
50
100
ns
15
ns
15
ns
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 7
ns
0.5tCK – 7
ns
0
20
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low1
5tCK
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t CKI
t CKIH
t CKIL
t CKOH
t CKH
t CKL
Figure 10. Clock Signals and Reset
–20–
REV. 0
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