ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
Parameter
PCI Bus Interface
Timing Requirements:
tVAL
CLK to Signal Valid
tON
CLK to Low-Z Delay
tOFF
CLK to High-Z Delay
tSU
tH
tRST-OFF
Input Setup to CLK
Input Hold After CLK
RST Active to Outputs High-Z
ADSP-2141L
Min
Max
Unit
2
11
ns
2
ns
28
ns
7
ns
1
ns
40
ns
CLK
OUTPUT
DELAY
THREE-STATE
OUTPUT
VTEST
t VAL
VSTEP (3.3V SIGNALING)
OUTPUT CURRENT Ơ… LEAKAGE CURRENT
t ON
t OFF
CLK
INPUT
t SU
tH
VTH
VTEST
INPUTS
VALID
VTEST
VTL
Figure 9. Output (Top) and Input Timing Measurement Conditions
VTH
VTL
VMAX
REV. 0
–19–
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