ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the timing specifications provided below are valid at
the DPI_P14–1 pins.
Table 24. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
2 × tPCLK – 1.2
ADSP-21467/ADSP-21469
Max
2 × (231 – 1) × tPCLK
Unit
ns
PWM
OUTPUTS
tPWMO
Figure 13. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DPI_P14–1 pins.
Table 25. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
2 × tPCLK
Max
2 × (231 – 1) × tPCLK
Unit
ns
TIMER
CAPTURE
INPUTS
tPWI
Figure 14. Timer Width Capture Timing
Rev. B | Page 29 of 76 | March 2013
Share Link: 
