ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
TIMING SPECIFICATIONS
Table 12 and Table 13 describe the timing requirements for the
ADSP-BF534/ADSP-BF536/ADSP-BF537 processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 15
describes phase-locked loop operating conditions.
Table 12. Core Clock Requirements—600 MHz Speed Grade1
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT =1.2 V minimum)
fCCLK
Core Clock Frequency (VDDINT =1.045 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.85 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.8 V )
600
MHz
475
MHz
425
MHz
375
MHz
250
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 25 and can also be seen on the specific products ordering guide. It stands for the
maximum allowed CCLK frequency at VDDINT = 1.2 V and the maximum allowed VCO frequency at any supply voltage.
Table 13. Core Clock Requirements—500 MHz Speed Grade1
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT = 1.2 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 1.045 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.85 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.8 V )
500
MHz
444
MHz
400
MHz
333
MHz
250
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 25 and can also be seen on the specific products ordering guide. It stands for the
maximum allowed CCLK frequency at VDDINT = 1.2 V and the maximum allowed VCO frequency at any supply voltage.
Table 14. Core Clock Requirements—400 MHz Speed Grade1
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT = 1.14 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 1.045 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.85 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.8 V )
400
MHz
363
MHz
333
MHz
280
MHz
250
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 25 and can also be seen on the specific products ordering guide. It stands for the
maximum allowed CCLK frequency at VDDINT = 1.2 V and the maximum allowed VCO frequency at any supply voltage.
Table 15. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Speed Grade1
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 25 and can also be seen on the specific products ordering guide. It stands for the
maximum allowed CCLK frequency at VDDINT = 1.2 V and the maximum allowed VCO frequency at any supply voltage.
Rev. B | Page 26 of 68 | July 2006
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