ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
SDRAM Interface Timing
Table 21. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
1.5
ns
0.8
ns
tSCLK
tSCLKH
CLKOUT Period1
CLKOUT Width High
7.5
ns
2.5
ns
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT2
Command, ADDR, Data Hold After CLKOUT2
Data Disable After CLKOUT
Data Enable After CLKOUT
2.5
ns
4.0
ns
1.0
ns
6.0
ns
1.0
ns
1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 16. Package type and reduced supply voltages affect the best-case value of 7.5 ns listed here.
2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
CLKOUT
DATA (IN)
DATA (OUT)
COMMAND ADDR
(OUT)
tSSDAT
tSCLK
tSCLKH
tHSDAT
tSCLKL
tENSDAT
tDCAD
tHCAD
tDSDAT
tDCAD
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. B | Page 31 of 68 | July 2006
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