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ADSP-BF534 View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-BF534
ADI
Analog Devices ADI
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Ports
Table 24 through Table 27 on Page 37 and Figure 19 on Page 37
through Figure 21 on Page 39 describe serial port operations.
Table 24. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSE
TFS/RFS Hold After TSCLK/RSCLK1
tSDRE
Receive Data Setup Before RSCLK1
tHDRE
Receive Data Hold After RSCLK1
tSCLKEW
TSCLK/RSCLK Width
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
Transmit Data Delay After TSCLK2
Transmit Data Hold After TSCLK2
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSI
TFS/RFS Hold After TSCLK/RSCLK1
tSDRI
Receive Data Setup Before RSCLK1
tHDRI
Receive Data Hold After RSCLK1
tSCLKEW
TSCLK/RSCLK Width
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSI
tHOFSI
tDDTI
tHDTI
tSCLKIW
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
Transmit Data Delay After TSCLK2
Transmit Data Hold After TSCLK2
TSCLK/RSCLK Width
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLK1
Data Disable Delay from External TSCLK1
Data Enable Delay from Internal TSCLK1
Data Disable Delay from Internal TSCLK1
1 Referenced to drive edge.
Rev. B | Page 36 of 68 | July 2006
Min
Max
Unit
3.0
ns
3.0
ns
3.0
ns
3.0
ns
4.5
ns
15.0
ns
10.0
ns
0
ns
10.0
ns
0
ns
Min
Max
Unit
8.0
ns
–1.5
ns
8.0
ns
–1.5
ns
4.5
ns
15.0
ns
3.0
ns
−1.0
ns
3.0
ns
−1.0
ns
4.5
ns
Min
Max
Unit
0
ns
10.0
ns
–2.0
ns
3.0
ns
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