ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Parallel Peripheral Interface Timing
Table 23 and Figure 15 on Page 33, Figure 19 on Page 37, and
Figure 20 on Page 38 describe parallel peripheral interface
operations.
Table 23. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width1
PPI_CLK Period1
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
1 PPI_CLK frequency cannot exceed fSCLK/2.
Min
Max
Unit
6.0
ns
15.0
ns
6.7
ns
1.0
ns
3.5
ns
1.5
ns
8.0
ns
1.7
ns
8.0
ns
1.8
ns
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
DATA
SAMPLING
EDGE
FRAME
SYNC
DRIVING
EDGE
DATA
SAMPLING
EDGE
tDFSPE
tHOFSPE
tSDRPE
tHDRPE
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. B | Page 33 of 68 | July 2006
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